1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of Related Art
Techniques have been proposed for forming uneven surfaces such as trenches in the channel region of a substrate, to increase the effective channel width of a transistor without increasing in size.
For example, Japanese Patent Laid-Open No. H11-103058 and Japanese Patent Laid-Open No. S51-147269 describe a semiconductor device including a trench gate structure in which trenches are formed on the substrate surface. Japanese Patent Laid-Open No. 2007-5568 describes a semiconductor device in which a plurality of projecting silicon regions are formed in the width direction of a channel region formed between a source region and a drain region which are formed on a semiconductor substrate. A gate insulating film and a gate electrode are formed facing the channel region on the silicon projections. A reduction in the pitch of the gates reduces the width of the projections and achieves full depletion of a depletion layer in the projections during the operation of transistors, thus mitigating the short channel effect and improving the subthreshold slope (Japanese Patent Laid-Open No. 2005-085960). It is also possible to use such a decrease in the substrate bias dependence of threshold voltage due to such full depletion to advantage in an appropriate circuit configuration.
Japanese Patent Laid-Open 2009-54999 describes a semiconductor device formed on a semiconductor substrate of a first conductivity type and equipped with a trench structure having a depth intermittently changing in the gate width direction, a gate electrode formed, via a gate insulating film, inside a trench portion defined by the trench structure and on the upper surface of a planar portion, a source region of a second conductivity type formed on one side of the gate electrode, and a drain region of a second conductivity type formed on the other side of the gate electrode. Portions of the source region and the drain region which face each other with the trench portion therebetween have a depth equal to or greater than the depth of the trench structure from the upper surface to the bottom portion. Due to this structure, a current which otherwise flows mainly around the upper surface of the recessed portion of the gate electrode starts flowing more uniformly through the whole trench portion, resulting in an increase in the effective gate depth of the recessed portion whose depth changes in the gate width direction. According to this document, a semiconductor device having such a configuration can have reduced on-resistance and enhanced transistor power.
Japanese Patent Laid-Open No. 2008-192985 describes a semiconductor device in which trench portions are formed in the gate width direction so as to provide a well with unevenness and a gate electrode is formed inside and on the upper surface of the trench portion via an insulating film. A source region is formed on one side of the gate electrode in the gate length direction and a drain region is formed on the other side. The source region and the drain region both have a depth reaching the vicinity of the bottom portion of the gate electrode (the vicinity of the bottom portion of the trench portion). By forming the source region and the drain region of such a depth, a current which otherwise flows mainly around a shallow portion of the gate electrode starts flowing more uniformly through the whole trench portion and an effective gate width increases due to the unevenness formed in the well. According to this document, a semiconductor device having such a configuration can have reduced on-resistance and enhanced transistor power.
Semiconductor devices obtained by extending a source region and a drain region to the vicinity of the bottom portion of the gate electrode as the configurations described in Japanese Patent Laid-Open No. 2008-192985 and 2008-192985 can be expected to have reduced on-resistance and enhanced transistor power.
The present inventors have however found that a problem occurs in a transistor having such a configuration in which a source region and a drain region are extended to the vicinity of the bottom portion of a gate electrode. The present inventors have found that in Vd−Id characteristics (drain voltage−drain current characteristics) of a transistor having such a configuration, an abnormal increase in Id occurs in a region where the drain voltage Vd is high. Measurement results of Vd−Id characteristics are shown in FIG. 22.
FIG. 23 illustrates the configuration of this semiconductor device. The semiconductor device illustrated herein includes a gate insulating film and a gate electrode 22 formed in a trench formed on a substrate and a channel 8 and a drain 13 formed on the substrate. The drain 13 is illustrated as one body in this diagram but may be comprised of a surface drain region having a high dopant concentration and an offset region formed below the drain region to cover it and having a low dopant concentration. A PN boundary line 30 is formed at the boundary between the drain 13 and the channel 8.
As illustrated in FIG. 22, particularly when a gate voltage Vg is 9V or greater, Id shows an abnormal increase (an area enclosed with a broken line in this diagram) from a drain voltage Vd of 15V or greater. The present inventors investigated a cause for this abnormality in the Vd−Id characteristics based on two-dimensional simulation. FIG. 23 shows the simulation results of a potential when a gate voltage (18V) and a drain voltage (16V) are applied to the gate electrode 22 and a drain electrode (not illustrated), respectively. It is apparent from the results that isoelectric lines are densely distributed at the lower corner of the trench of the gate electrode 22, suggesting electric field concentration. The present inventors have found that abnormality occurs in the Vd−Id characteristics because when the PN boundary line 30 between the drain 13 and the channel 8 exists in the vicinity of the lower corner of the trench, respective applications of a predetermined gate voltage and a predetermined drain voltage to the gate electrode 22 and the drain electrode cause electric field concentration at the lower corner of the trench, generate hot carriers at this portion markedly, and cause impact ionization to allow a substrate current to flow between the drain 13 and the substrate. Generation of such hot carriers deteriorates the long term reliability of the device.